Integration method of a semiconductor device having a recessed gate electrode

ABSTRACT

Embodiments of the invention are directed to an integrated circuit device and a method for forming the device. In some embodiments of the invention, two types of transistors are formed on a single substrate, transistors: transistors having a recessed gate, and transistors having a planer gate electrode. In other embodiments, transistors having a recessed gate are formed in multiple areas of the same substrate. Additionally, gates of the transistors in more than one region may be formed simultaneously.

This is a Divisional of U.S. patent application Ser. No. 10/649,262,filed on Aug. 26, 2003, now pending, which claims priority from KoreanPatent Application No. 2003-48079, filed on Jul. 13, 2003, which isincorporated by reference in is entirety.

TECHNICAL FIELD

This disclosure relates to an integration manufacturing method of asemiconductor memory device such as a Dynamic Random Access Memory(DRAM), and, more specifically, to a method to produce DRAM cells havinga recessed gate and a planer gate electrode.

BACKGROUND

Integrated circuits, such as ultra-large scale integrated (ULSI)circuits, can include as many as one billion transistors or more. Mosttypically, ULSI circuits are formed of Field Effect Transistors (FETs)formed in a Complementary Metal Oxide Semiconductor (CMOS) process. EachMOSFET includes a gate electrode formed over a channel region of thesemiconductor substrate, which runs between a drain region and sourceregion. To increase the device density and operation speed of theintegrated circuits, the feature size of transistor within the circuitsmust be reduced. However, with the continued reduction in device size,sub-micron scale MOS transistors have to overcome many technicalchallenges. As the MOS transistors become narrower, that is, theirchannel length decreases, problems such as junction leakage,source/drain breakdown voltage, and data retention time become morepronounced.

One solution to decrease the physical dimension of ULSI circuits is toform recessed gate or “trench-type” transistors, which have a gateelectrode buried in a groove formed in a semiconductor substrate. Thistype of transistor reduces short channel effects by effectivelylengthening the effective channel length by having the gate extend intothe semiconductor substrate. An example of a portion of a combined ULSIcircuit including a standard transistor and a recessed gate transistoris illustrated in FIG. 1. However, effectively forming recessed gatetransistors in ULSI circuits that also contain non recessed gatetransistors has been a difficult task.

Embodiments of the invention address these and other problems in theprior art.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be understood more fully from the detaileddescription given below and from the accompanying drawings ofembodiments of the invention, which, however, should not be taken tolimit the invention to the specific embodiments, but are to facilitateexplanation and understanding.

FIG. 1 is a cross-sectional diagram of a MOSFET having a recessed gateaccording to the prior art.

FIGS. 2, 3, 4, 5A, 6A and 7A are cross-sectional diagrams of a method offorming a MOSFET with a recessed gate and a planer gate electrodeaccording to an embodiment of the present invention.

FIGS. 5B and 6B are cross-sectional diagrams illustrating alternativeprocesses that were illustrated in FIGS. 5A and 6A, respectively.

FIG. 7B is a cross-sectional diagram illustrating another alternativeprocess that was illustrated in FIG. 7A.

FIGS. 8 to 12 are cross-sectional diagrams illustrating a method offorming a MOSFET having a recessed gate and a planer gate electrodeaccording to another embodiment of the present invention.

FIGS. 13 to 17 are cross-sectional diagrams illustrating a method offorming a MOSFET having a recessed gate and a planer gate electrodeaccording to yet another embodiment of the present invention.

FIGS. 18 to 22 are cross-sectional diagrams illustrating of a method offorming a MOSFET having a recessed gate transistor in a cell region anda recessed gate in a peripheral region of a semiconductor substrateaccording to still a further embodiment of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

In the following detailed descriptions, numerous specific details areset forth in order to provide a thorough understanding of the invention.However, it will be understood by those skilled in the art that thepresent invention may be practiced without these specific details. Inother instances, well-known methods, procedures, components and circuitshave not been described in detail so as not to obscure the presentinvention.

Embodiments of the invention can provide, compared to conventionalmemory circuits, an increase in effective channel length, a decrease inchannel dosing, and improved qualities in junction leakage and dataretention time in a memory circuit that includes at least two types oftransistors on a single substrate: transistors having a recessed gate,and transistors having a planer gate electrode.

A manufacturing method of a semiconductor device of an embodiment of thepresent invention is described with reference to FIGS. 2 to 7. As shownin FIG. 2, a semiconductor device according to embodiments of thepresent invention includes a memory cell array section A and aperipheral circuit section B. The memory cell array section isillustrated in the left-had portion of the figures, while the peripheralcircuit section is illustrated in the right-hand portion.

An isolation region 15 is formed on a silicon substrate 10. A thin padoxide film 18 is formed on the isolation 15 and over an active region inthe memory cell array section. An etch stopper layer 20 is formed on thepad oxide film 18. The etch stopper layer 20 is preferably made ofnitride, for example SiN, with a thickness of about 100 to 200angstroms. A first oxide layer 25 is formed on the etch stopper layer20. The first oxide layer 25 can be formed to a thickness ofapproximately 1000 angstroms in some embodiments.

A recess mask, for forming the recessed gates for the memory cells isformed in a photoresist layer 30 by conventional photolithography andetching processes. As shown in FIG. 3, a recess gate hole 28 is formedin the memory cell side of the substrate 10 by etching the first oxidelayer 25, the pad oxide 18, and the etch stopper layer 20. On theperipheral side of the substrate 10, the first oxide layer 25, the padoxide 18, and the etch stopper layer are all removed.

As shown in FIG. 4, a gate oxide 35 is formed on the silicon substrate10 and within the recess holes 28. A gate electrode layer is formed onthe gate oxide 35. The gate electrode layer is formed as a two layerstructure including a lower gate electrode poly layer 40 and an uppergate electrode layer 45, which could be, for example, Wsi. Next, a gatemask layer 50 is formed on the upper gate electrode layer 45. As shownin FIG. 5A, the gate electrode is completed by performing conventionalphotolithography and etching processes on the gate mask layer 50, theupper gate electrode 45, and the gate oxide layer 35.

Next, as illustrated in FIG. 6A, a deposited insulating layer is etchedback to form a spacer 60. Finally, as illustrated in FIG. 7A, a Cosi(Cobalt-Silicon) layer 70 is formed on the peripheral circuit region.The Cosi layer 70 reduces sheet resistance in the peripheral region.

Some alternative methods for forming the memory circuit according toembodiments of the invention are illustrated in FIGS. 5B, 6B, and 7B. Asshown in FIGS. 5B and 6B, the first oxide layer 25 and gate oxide 35 areremoved from areas other than under the gate stack in the cell region(FIG. 5B), and gate stack spacers 60 are formed around the gate stack(FIG. 6B). FIG. 6B is similar to FIG. 6A, except for the removed oxidelayer 25, etch stopper layer 20 and pad oxide layer 18. FIG. 7B showsthat another alternative embodiment is to add the spacers 60 beforeetching the oxide layer 25, etch stopper layer 20 and pad oxide layer18.

Another embodiment of forming a semiconductor memory device isillustrated in FIGS. 8-12. As shown in FIG. 8, a semiconductor deviceaccording to embodiments of the present invention includes a memory cellarray section A and a peripheral circuit section B. An isolation region15 is formed on a silicon substrate 10. A thin pad oxide film 18 isformed on the isolation 15 and over an active region in the memory cellarray section. An etch stopper layer 20 is formed on the pad oxide film18. The etch stopper layer 20 is preferably made of nitride, for exampleSiN, with a thickness of about 100 to 200 angstroms. A first oxide layer25 is formed on the etch stopper layer 20.

A recess mask for forming the recessed gates for the memory cells isformed in a photoresist layer 30 by conventional photolithography andetching processes. As shown in FIG. 9, a recess gate hole 28 is formedin the memory cell side of the substrate 10 by wet etching the firstoxide layer 25, the etch stopper layer 20, and the pad oxide layer 18.As shown in FIG. 10, a gate oxide 35 is formed on the silicon substrate10 and within the recess holes 28. A gate electrode having a two layerstructure formed of a lower gate electrode poly 40 and an upper gateelectrode Wsi 45 is formed on the gate oxide 35. A gate mask layer 50 isformed on the Wsi layer. As compared to FIG. 4, described above, FIG. 10illustrates that the lower gate electrode layer 40, the upper gateelectrode Wsi layer 45, and the gate mask layer 50 are all at evenlevels in both the peripheral area and the cell area of thesemiconductor substrate 10.

As shown in FIG. 11, a gate electrode is formed by conventionalphotolithography and etching processes. Next, as illustrated in FIG. 12,a spacer 60 is formed that covers the gate structures in the cell areaand the peripheral area of the semiconductor substrate 10.

A further embodiment of forming a semiconductor memory device isillustrated in FIGS. 13-17. As shown in FIG. 13, a semiconductor deviceaccording to embodiments of the present invention includes a memory cellarray section A and a peripheral circuit section B. An isolation region15 is formed on a silicon substrate 10. A thin pad oxide film 18 isformed on the isolation 15 and over an active region in the memory cellarray section. An etch stopper layer 20 is formed on the pad oxide film18. The etch stopper layer 20 is preferably made of nitride, for exampleSiN, with a thickness of about 100 to 200 angstroms. A first oxide layer25 is formed on the etch stopper layer 20. The first oxide layer 25 isformed thicker than illustrated in FIGS. 2 and 8, and is formed to aheight roughly equal to the height of a gate stack in the peripheralregion of the substrate 10.

A photoresist layer 30 is formed over the first oxide layer 25. Next, arecess mask for forming the recessed gates for the memory cells and forforming a planer gate hole 29 (FIG. 14) is formed in a photoresist layer30, by conventional photolithography and etching processes. Then, therecess gate hole 28 is formed in the first oxide layer 25, etch stopperlayer 20, and the pad oxide layer 18, as well as the silicon substrate10. Additionally, the planer gate hole 29 is formed in the first oxidelayer 25 on the peripheral portion of the substrate 10 by an etchingprocess.

The first oxide layer 25 on the peripheral side of the substrate 10 isthicker than the first oxide layer 25 on the cell region portion of thesubstrate 10.

Next, as shown in FIG. 15, a gate oxide 35 is formed by oxidationprocess on the substrate 10 and within the recess hole 28 and planerhole 29. A gate electrode stack having a two layer structure is thenformed on the gate oxide 35. The gate electrode stack is formed of alower gate electrode poly layer 40 and an upper gate electrode Wsi layer45.

As illustrated in FIG. 16, a gate layer mask 50 is formed on the Wsilayer within the recess hole 28 and the planer hole 29. Then, the firstoxide layer 25 is removed in areas not covered by the gate layer mask 50by, for example, a wet etch process. Finally, as illustrated in FIG. 17,spacers 60 are formed on the gate stacks in the cell region and in theperipheral region of the semiconductor substrate.

Yet further methods to form a semiconductor memory device areillustrated in FIGS. 18-22. As shown in FIG. 18, a semiconductor deviceaccording to embodiments of the present invention includes a memory cellarray section A and a peripheral circuit section B. An isolation region15 is formed on a silicon substrate 10. A thin pad oxide film 18 isformed on the isolation 15 and over an active region in the memory cellarray section. An etch stopper layer 20 is formed on the pad oxide film18. The etch stopper layer 20 is preferably made of nitride, for exampleSiN, with a thickness of about 100 to 200 angstroms.

A first oxide layer 25 is formed on the etch stopper layer 20. Next, arecess mask 30 is formed by conventional photolithography and etchingprocesses. As shown in FIG. 19, a recess gate hole 28 is formed by etchprocess in the memory cell region and in the peripheral region of thesubstrate 10. Next, as shown in FIG. 20, a gate oxide 30 is formed by,for example, an oxidation process in the recess holes 28.

As illustrated in FIG. 20, a gate electrode layer is formed on the gateoxide 35. The gate electrode layer of FIG. 20 has a two layer structureformed of a lower gate electrode poly 40 and an upper gate electrode Wsi45. In this embodiment, the lower gate electrode poly 40 extends intothe recessed gate holes in the cell region and in the peripheral regionof the substrate 10. A gate mask layer 50 is formed on the Wsi layer.

As shown in FIG. 21, a set of gates is formed by conventionalphotolithography and etching processes in the cell region and theperipheral region. Finally, as illustrated in FIG. 22, a spacer 60 isformed by, for example, an etch back process.

As described above in detail, in embodiments of the present invention, arecessed gate cell and a planer gate electrode are simultaneously formedin the same photolithography step. This allows memory circuits to bedeveloped so that the manufacturing processes will be reasonable withoutincreasing the number of the photolithography steps.

Those skilled in the art recognize that the method of forming integratedcircuits described herein can be implemented in many differentvariations. Therefore, although various embodiments are specificallyillustrated and described herein, it will be appreciated thatmodifications and variations of the present invention are covered by theabove teachings and within the purview of the appending claims withoutdeparting from the spirit and intended scope of the invention

1. A memory device, comprising: a substrate divided into a memory cellregion and a peripheral circuit region; a plurality of memory cellshaving recessed gates formed in the memory cell region; and at least onetransistor in the peripheral circuit region, the transistor including: achannel region formed between a source region and a drain region, a gatestructure disposed over the channel region, and a resistance-reducinglayer formed over the source and drain regions.
 2. The memory device ofclaim 1 wherein the resistance-reducing layer comprises Cobalt.
 3. Thememory device of claim 2 wherein the resistance-reducing layer comprisesa Cobalt-Silicon material.
 4. The memory device of claim 1, furthercomprising an epitaxially grown silicon structure disposed between thesource and drain regions and the resistance-reducing layer.
 5. Thememory device of claim 4 wherein the epitaxially grown silicon structureis formed by SEG (Selective Epitaxial Growing).
 6. A memory devicecomprising: a substrate divided into a cell region and a peripheralregion; a plurality of memory cells formed in the cell region, theplurality of memory cells each having a recessed gate structure; and aplurality of transistors in the peripheral region, the plurality oftransistors each having a recessed gate structure.
 7. The memory deviceof claim 6 wherein gates of the memory cells in the cell region andgates of the cells in the peripheral region are formed simultaneously.